1. Field
Example embodiments relate to methods of forming a wiring structure for integrated circuit devices and methods of manufacturing non-volatile semiconductor devices having the same, and more particularly, to methods of forming the wiring structure by a spacer patterning process and methods of manufacturing non-volatile semiconductor devices using the same.
2. Description of the Related Art
As the degree of integration of integrated circuit devices increases, conductive structures and wiring structures may be downsized and/or become more dense. The downsizing of the structures usually reduces the cross sectional area of the wiring structure and thus increases electrical resistance in the wiring structures of the semiconductor devices. In addition, the high density of the structures on a substrate usually causes a RC delay (resistance-capacitance delay) and an electronic interference between neighboring conductive structures and wiring structures of the semiconductor devices. Thus, the high degree of the integration may increase failures of the devices, and various research has been conducted for reducing device failures in parallel with studies for increasing the degree of integration.
For example, it has been suggested that copper (Cu) having a relatively low electrical resistance may be used for a wiring material and a low-k dielectric material having a relatively low dielectric constant may be used for an insulation interlayer.
Particularly, copper (Cu) may offer advantages of higher electrical conductivity and lower electro-migration as compared with aluminum (Al), which has been most widely used as a wiring structure in semiconductor devices. Thus, the low resistance property of the copper (Cu) may reduce an RC delay of the wiring structure to thereby reduce and/or minimize the reduction of the operation speed and power consumption of the semiconductor device. In addition, the lower electro-migration of the copper (Cu) may reduce and/or minimize the process limitations and reduce process failures of the semiconductor device, to thereby increase production yield of the semiconductor device.
However, copper (Cu) may present difficulties in patterning through conventional patterning processes including deposition processes for forming a thin layer and etching processes for etching the thin layer. For those reasons, a damascene process has been used for forming a copper pattern in which a recessed portion corresponding to the wiring structure is firstly formed in an insulation interlayer and the recessed pattern is filled with copper (Cu). That is, an insulation interlayer is first patterned to have an opening portion such as a via-hole and a trench therein, and a copper layer is formed on the insulation interlayer to a sufficient thickness to fill up the opening. Then, the copper layer may be removed from the insulation interlayer by a planarization process until a top surface of the insulation interlayer is exposed and thus the copper layer remains in the opening to form the copper wiring structure.
The above conventional damascene process may become more difficult to perform as the degree of integration of a semiconductor device increases. Conventionally, the recessed pattern having the via-hole or the trench is usually formed in the insulation interlayer by a photolithography process using a photolithography pattern on the insulation interlayer as a mask pattern. However, it may be difficult to form fine patterns in the insulation interlayer due to the resolution limitations of the lithography apparatus. In particular, it may be difficult to form fine patterns having a critical dimension (CD) of less than about 40 nm, because the theoretical CD limit for the photolithography process may be about 46 nm. Therefore, the conductive structures such as gate lines and wiring structure for recent very high integrated semiconductor device may be very difficult to form using present photolithography apparatus.
Accordingly, a double patterning technology (DPT) or a spacer patterning technology (SPT) has been suggested for forming fine patterns having a CD of less than the minimum resolution of the photolithography apparatus through consecutive photolithography processes.
In a conventional structure of the semiconductor devices, memory cells including conductive structures and wiring structures may be arranged in a cell area of a chip, and peripheral circuits for applying an electrical power and/or control signals to the memory cells may be arranged in a peripheral/core area of the chip, and a line width of a pattern in the cell area may be different from that of a pattern in the peripheral/core area. Based on the conventional structure of the semiconductor device, the DPT or the SPT performs a double exposure using a first mask pattern having a relatively small pitch and a second mask pattern having a pitch larger than that of the first mask pattern. Therefore, a first pattern having a relatively small line width or a relatively small interval is formed in the cell area of a substrate by a first photolithography process using the first mask pattern and a second pattern having a relatively large line width or a relatively large interval is formed in the peripheral/core cell area of a substrate by a second photolithography process using the second mask pattern. The DPT or the SPT process is usually performed in such a way that the first pattern has a line width smaller than the marginal resolution of the photolithography apparatus simultaneously with the second pattern of which the line width is larger than the marginal resolution of the photolithography apparatus. Therefore, the conductive structures and the wiring structures of which the line widths are varied to be smaller or larger than the marginal resolution (for example, in accordance with the cell area and the peripheral/core area) may be formed on the substrate simultaneously with each other by the DPT or the SPT process.
However, when the mask patterns used in the first and the second photolithography processes are not properly positioned on the substrate, the conductive structures or the wiring structures including both of the first and second patterns cannot be formed on the substrate. For example, in a cell area of a NAND flash memory device in which a plurality of bit lines is arranged between a string selection line (SSL) and a ground selection line (GSL), it may be describable to form each of the bit lines as a fine pattern having a line width smaller than the marginal resolution of the photolithography apparatus. Also, a node separation pattern connected to a group of the bit lines at end portions thereof may be formed into a normal pattern having a line width larger than the marginal resolution of the photolithography apparatus. Thus, the bit lines of the NAND flash memory device may be formed in the cell area of the substrate by a first damascene process using the first mask pattern, and the node separation patterns may be formed in the same cell area of the substrate by a second damascene process using the second mask pattern in a similar manner as the photolithography process for forming the wiring structures in the peripheral/core area of the substrate.
In such a case, when a first damascene position to which the first photolithography process is performed using the first mask pattern is not aligned with a second damascene position to which the second photolithography process is performed using the second mask pattern, the bit lines may not be connected to a proper node separation pattern. Thus, the bit lines neighboring to each other may make contact with each other.
Further, a spacer pattern for forming the first pattern in the cell area may be damaged in a second etching process using the second mask pattern as an etching mask in the peripheral/core area of the substrate. In a conventional DPT or SPT process, the spacer pattern may be formed in the cell area of the substrate by a first etching process using the first mask pattern as an etching mask, and then a supplementary mask pattern for forming the second pattern may be formed in the peripheral/core area by the second etching process. Thus, the spacer pattern in the cell area may be damaged in the second etching process, and the first damascene process using the spacer pattern as an etching may be insufficiently performed. For those reasons, the widths of the via-holes or the trenches may become non-uniform and thus the line widths the bit lines, which are usually formed in the via-holes or the trenches, may also become non-uniform.